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The twin-transistor noise-tolerant dynamic circuit technique

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2 Author(s)
Balamurugan, G. ; Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA ; Shanbhag, N.R.

This paper describes a new circuit technique for designing noise-tolerant dynamic logic. It is shown that voltage scaling aggravates the crosstalk noise problem and reduces circuit noise immunity, motivating the need for noise-tolerant circuit design. In a 0.35-μm CMOS technology and at a given supply voltage, the proposed technique provides an improvement in noise immunity of 1.8×(for an AND gate) and 2.5×(for an adder carry chain) over domino at the same speed. A multiply-accumulate circuit has been designed and fabricated using a 0.35-μm process to verify this technique. Experimental results indicate that the proposed technique provides a significant improvement in the noise immunity of dynamic circuits (>2.4x) with only a modest increase in power dissipation (15%) and no loss in throughput

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Solid-State Circuits, IEEE Journal of  (Volume:36 ,  Issue: 2 )