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A 10-b 185-MS/s track-and-hold in 0.35-μm CMOS

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3 Author(s)
A. Boni ; Dipt. di Ingegeneria dell'Inf., Parma Univ., Italy ; A. Pierazzi ; C. Morandi

This paper discusses the design and the implementation of a high-speed track-and-hold amplifier in 0.35-μm CMOS, featuring 10-b resolution up to 185 MS/s. The implemented folded-cascode input buffer allows a relatively large input range, 1-Vpp differential, and low harmonic distortion at the same time. The sampler is based oh a switched-source-follower (SSF) architecture with double switch-off action and saturation-mode switches, providing short aperture times and high linearity. A spur-free dynamic range (SFDR) of 63 dB at 185 MS/s was measured with a dual-tone 45-MHz±250-kHz test signal. The open-loop architecture makes harmonic distortion little sensitive to the input frequency: 10-b resolution is maintained up to 45 MHz with 1 Vpp and up to 70 MHz with 0.7 Vpp. A suitable hold-mode feedthrough rejection is achieved by means of feedforward cancellation with a MOS capacitor operating in depletion or accumulation. The track-and-hold amplifier consumes 70 mW from a 3.3-V supply

Published in:

IEEE Journal of Solid-State Circuits  (Volume:36 ,  Issue: 2 )