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Scaling up of wave pipelines

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4 Author(s)
Fukase, M. ; Dept. of Electron. & Inf. Syst. Eng., Hirosaki Univ., Aomori, Japan ; Sato, T. ; Egawa, R. ; Nakamura, T.

Wave pipelining is a technique of arranging synchronous logic circuits in a pipeline fashion based on delay balancing that allows clocking rate higher than that of well-known regular pipelining. In order to scale up wave-pipelined circuits in the trend of VLSI development toward tighter integration, firstly we investigate scale-dependent characteristics of those circuits with simple structure. It is shown that larger scale is more favorable in view of pipeline degree and vector-execution time. Secondly we explore multifunctional wave pipelines with considerable scales and complicated structures. A fully wave-pipelined structure is recommended to multifunctional circuits regarding software overheads and areas. Thirdly, we show the standard cell synthesis of a fully wave-pipelined scalar processing unit to demonstrate the practicality of wave pipelining multifunctional random logic circuits. By using 0.5-μm CMOS technology, a scalar processing unit is implemented in a 2.3-mm×2.3-mm chip whose clock speed is estimated to be 1 GHz from circuit level simulation

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VLSI Design, 2001. Fourteenth International Conference on

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