By Topic

High level synthesis of multi-precision data flow graphs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Agrawal, V. ; Supercomput. Educ. & Res. Centre, Indian Inst. of Sci., Bangalore, India ; Pande, A. ; Mehendale, M.M.

A number of DSP algorithms involve linear transforms employing weighted sum computations, where the weights are fixed at design time. Add-shift implementation of such a computation results in a data flow graph that has multiple precision variables and functional units. We explore the potential of precision sensitive approach for the high level synthesis of such multi-precision DFGs. We focus on fixed latency implementation of these DFGs. We present register allocation, functional unit binding and scheduling algorithms to exploit the multi-precision nature of such DFGs for area efficient implementation. The proposed approach is fairly generic and could be applied to multi-precision DFGs involving any type of functional units. Significant improvements of upto 27% have been obtained over the conventional high-level synthesis approach

Published in:

VLSI Design, 2001. Fourteenth International Conference on

Date of Conference: