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Early evaluation of bus interconnects dependability for system-on-chip designs

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3 Author(s)
Lajolo, M. ; NEC Res. Inst., Princeton, NJ, USA ; Reorda, M.S. ; Violante, M.

This paper presents a methodology for designing system-on-chip interconnection architectures providing a high level of protection from crosstalk and single-event upsets. An event driven simulator enriched with fault injection capabilities is exploited to evaluate the dependability level of the system being designed. The simulation environment supports several bus coding protocols and thus designers can easily evaluate different design alternatives. To enhance the dependability level of the interconnection architecture, we propose a distributed bus guardian scheme, where dedicated hardware modules monitor the integrity of the information transmitted over the bus and provide error correction mechanisms. Preliminary experimental results on a small benchmark system are reported showing the effectiveness of the proposed methodology

Published in:

VLSI Design, 2001. Fourteenth International Conference on

Date of Conference:

2001

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