By Topic

A novel algorithm for multi-node bridge analysis of large VLSI circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Zachariah, S.T. ; Archit. Group, Intel Corp., Santa Clara, CA, USA ; Chakravarty, S.

Defects that short two or more modes are known as multinode bridges. Multinode bridge analysis can be used to extract a list of either only two-node bridges or multi-node bridges. We discuss why multi-node bridge analysis is also required even if only two-node bridges are targeted. We propose a novel, scalable and accurate algorithm for multinode bridge analysis of large layouts. CARAFE can perform multi-node analysis only on small layouts. Comparison results show that for small layouts our algorithm is considerably faster than CARAFE. For larger layouts experimental results are provided to illustrate the performance and capacity of our algorithm

Published in:

VLSI Design, 2001. Fourteenth International Conference on

Date of Conference: