Cart (Loading....) | Create Account
Close category search window

Application specific macro based synthesis

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Sundararaman, S. ; DDEL, Cincinnati Univ., OH, USA ; Govindarajan, S. ; Vemuri, R.

This paper presents a novel approach to optimize the performance of a design synthesized from a given behavioral application. The high-level synthesis process is highly restricted by a pre-characterized library from which components are chosen to implement operations in the behavior. Moreover logic optimization on the register-transfer level datapath is typically limited to within the register boundaries that enclose the chosen components. It is imperative that the datapath components be carefully selected and synthesized in order to obtain a performance gain. The technique presented in this paper consists of two primary steps, application-specific macro generation and replacement, that are performed prior to high-level synthesis, The macro generation step extracts macro subgraphs from the given application graph and generates a macro component (an equivalent netlist)for each macro subgraph. Further; each macro component is optimized for performance using commercial logic synthesis tools. Using the enriched component library, a macro replacement step modifies the behavioral graph such that some subgraphs are replaced by equivalent macros. The replacement step attempts to replace subgraphs such that the design latency is minimized. The modified behavioral graph along with the enriched component library is then taken through high-level, logic and layout synthesis. Experiments on DSP benchmarks show that the macro based synthesis process achieves significant improvement in design performance as opposed to the traditional design process. We have developed an automated performance-optimization framework that is only limited by the optimization capability of backend tools

Published in:

VLSI Design, 2001. Fourteenth International Conference on

Date of Conference:


Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.