Cart (Loading....) | Create Account
Close category search window
 

Accurate power macro-modeling techniques for complex RTL circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Potlapally, N.R. ; Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA ; Raghunathan, A. ; Lakshminarayana, G. ; Hsiao, M.S.
more authors

This paper presents novel techniques for the cycle-accurate power macro-modeling of complex RTL components. The proposed techniques are based on the observation that RTL components often exhibit significantly different “power behavior” for different parts of the input space, making it difficult for a single conventional macro-model to accurately estimate the power dissipation over the entire input space. We address this problem by identifying and separating the input space into regions that display “similar” power behavior. We refer to these regions as the power modes of the component. We then construct separate macro-models for each region, and construct a function that, given the input trace to the component, selects an appropriate power mode (and hence macro-model) for use in each cycle. The proposed ideas are complementary to, and improve upon, previously proposed techniques for power macro-modeling such as linear regression, table look-up, power sensitivity, etc. We present experimental results on several practical complex RTL components, and demonstrate that the proposed techniques result in significant reductions (up to 90%) in the error of RTL macro-modeling compared to a gate-level power estimator

Published in:

VLSI Design, 2001. Fourteenth International Conference on

Date of Conference:

2001

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.