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Optimal assignment of high threshold voltage for synthesizing dual threshold CMOS circuits

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4 Author(s)
Tripathi, N. ; Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India ; Bhosle, A. ; Samanta, D. ; Pal, A.

Development of the process technology for dual threshold (dual V th) CMOS circuit has opened up the possibility of using it to reduce static power in low voltage high performance circuits. It has been demonstrated that by using transistors of a low threshold voltage for gates on the critical path, and by using a high threshold voltage for gates in the off-critical path it is possible to significantly reduce leakage power consumption of a circuit without performance degradation. In this paper we have a new algorithm to realize dual CMOS circuits. Our algorithm produces significantly better results for ISCAS benchmark circuits compared to reported results

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VLSI Design, 2001. Fourteenth International Conference on

Date of Conference: