Cart (Loading....) | Create Account
Close category search window
 

Synthesis of system-on-a-chip for testability

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Ravi, S. ; Dept. of Electr. Eng., Princeton Univ., NJ, USA ; Jha, N.K.

System synthesis takes an abstract system-level description as its input and produces a system-on-a-chip (SOC) as its output. Emphasis during synthesis is usually on optimizing one or more objectives such as price, area, performance and power. Testability enhancement of the SOC solution so obtained follows as a postprocessing step to enable the application of precomputed test sequences to each embedded core and observe its responses. Unfortunately, cascading test synthesis to an SOC synthesis framework does not usually preserve the optimality of the solution obtained. The work presented here describes the first method that incorporates finite-state automata (FSA) based symbolic testability analysis within the framework of system synthesis to address the above shortcoming. Unlike many existing SOC test approaches, FSA based testability analysis facilitates low test overheads and test application times without sacrificing the test coverage of the embedded cores. Our experimental work with an existing multi-objective optimization algorithm and a system-level test framework for a number of examples indicate that efficient SOC architectures, which trade off different architectural features such as integrated circuit price, power consumption, area and/or testability costs under real-time constraints, can be easily generated

Published in:

VLSI Design, 2001. Fourteenth International Conference on

Date of Conference:

2001

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.