By Topic

Testable design of sequential circuits with improved fault efficiency

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Das, D.K. ; Dept. of Comput. Sci. & Eng., Jadavpur Univ., Calcutta, India ; Bhattacharya, B.B. ; Ohtake, S. ; Fujiwara, H.

A new synthesis and design-for-testability (DFT) technique is proposed for improving fault efficiency in non-scan synchronous sequential circuits. Certain simple constraints are imposed on state encoding prior to synthesis, and then a DFT technique is employed that guarantees absence of all sequentially undetectable faults, such as invalid, equivalent and isomorph. If the netlist is available instead of state description, only the DFT technique is applied, by skipping the synthesis part. The proposed design guarantees significantly lower test generation time, higher fault coverage, and almost complete fault efficiency, when sequential test generation tools are used. Experiments on MCNC and ISCAS 89 benchmark circuits show encouraging results. Hardware overhead of the proposed method compares favorably with that of full-scan

Published in:

VLSI Design, 2001. Fourteenth International Conference on

Date of Conference:

2001