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On improving static test compaction for sequential circuits

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3 Author(s)
Ruifeng Guo ; Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA ; Pomeranz, I. ; Reddy, S.M.

The cost of testing a VLSI circuit is greatly affected by the length of its test sequence. Compaction techniques are often used to reduce the test sequence length. In this paper, we propose a new test sequence compaction procedure for synchronous sequential circuits aimed at improving the level of compaction compared to earlier efficient procedures. It is based on the reverse order restoration (ROR) compaction algorithm and the vector omission based compaction algorithm presented earlier. During vector restoration, once a subsequence is restored, the vector omission based method is applied to the restored subsequence to reduce the number of test vectors restored. Parallel pattern simulation for a single fault, as proposed earlier, is used to speed up the vector restoration process. Experimental results on test sequences generated by several test generators show the effectiveness of the proposed method in improving the level of compaction

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VLSI Design, 2001. Fourteenth International Conference on

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