Cart (Loading....) | Create Account
Close category search window
 

The hierarchical concurrent flow graph approach for modeling and analysis of design processes

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Sahula, V. ; Dept. of Electron. & Commun. Eng., Regional Eng. Coll., Jaipur, India ; Ravikumar, C.P.

In this paper, we expose a new technique for the analysis of design flows. The modern-day chip design process is a complex one, with the following characteristics: (a) the execution times of individual tasks are difficult to predict, since a tool may occasionally produce unsatisfactory results, requiring the designer to repeat the task, (b) the increasing pressure on the project management to cut down the time-to-market forces the management to employ concurrent design techniques, and (c) the VLSI design flow is hierarchical, and a completely flat representation of the design flow is too complex to analyze. Existing techniques for design flow analysis cannot deal with the problems mentioned above. The hierarchical concurrent flow graph (HCFG) presented in this paper is an analysis technique which borrows the idea of graph transmittance from circuit theory and extends the concept to include hierarchy, concurrency and stochastic variation in task execution times. We apply the HCFG technique to analyze two realistic design flows. We show that a project manager can carry out a pre-execution “what-if” analysis to determine the best design flow management strategy, that is most likely to lead to the lowest execution time

Published in:

VLSI Design, 2001. Fourteenth International Conference on

Date of Conference:

2001

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.