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Evaluation of an advanced wafer carrier for ILD planarization

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4 Author(s)
Jaso, M. ; Dominion Semicond., Manassas, VA, USA ; Glynn, T. ; Giunta, J. ; Diefenderfer, D.

The ground rule reduction of the dimensions used in semiconductor manufacturing has increased the number of yielding devices extending into the 3 mm edge exclusion area on the wafer. The use of a conventional topring for interlevel dielectric chemical-mechanical planarization was evaluated against an advanced topring. The advanced topring was designed to improve the post planarization film uniformity in the edge region. The use of the advanced topring for interlevel dielectric polishing was shown to improve the uniformity of polished films in this region. The improved film uniformity and edge profile resulted in increased device yield

Published in:

Advanced Semiconductor Manufacturing Conference and Workshop, 2000 IEEE/SEMI

Date of Conference:

2000