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Effects of operator grouping on the VLSI final test facility layout scale

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3 Author(s)
Nakamae, Koji ; Fac. of Eng., Osaka Univ., Japan ; Koga, W. ; Fujioka, Hiromu

The effects of operator grouping on the final test facility layout scale have been evaluated in the final test process of one-chip microcomputer through an event-driven simulation analysis. As human resources, 4 kinds of operators, Leader, Operator α, Operator β, and Maintenance operator are considered. Leader and Operator α can operate any kind of machines in the final test process, but Operator β can operate limited kinds of machines. Three groupings of operators, Group 1, Group 2 and Group 3 are investigated. Groups 1 and 2 mainly consist of Operator β, though operators in Group 1 are more specialized than those in Group 2. Group 3 consists of Operator α. The simulation was applied to the final test facility layouts with three different scales (small, medium, and large). Simulated results show that as the layout scale becomes larger, the cost per chip is lowered and an advantageous grouping is changed from Group 3 to Group 1. Though Group 3 can process the greatest number of planned lots with the lowest average turnaround time, it needs the maximum number of operators and heightens the cost per chip. The effect of changes in the number of operators was also investigated. Results show that as the layout scale becomes larger, the effect of its variations is reduced and Group 3 is most unsusceptible to the variations in the number of operators

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Advanced Semiconductor Manufacturing Conference and Workshop, 2000 IEEE/SEMI

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