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Automatic test pattern generation with branch testing

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3 Author(s)
Makki, R.Z. ; Dept. of Electr. Eng., North Carolina Univ., Charlotte, NC, USA ; Bou-Ghazale, A. ; Tianshang, C.

The authors present a test algorithm for finite state machines called branch testing. Based on branch testing, a design-for-test (DFT) method is proposed. Comparisons to other DFT methods show the method to be competitive relative to circuit overhead. A minimum set of paths containing all primary and internal gate-level input/output lines is found. Each of these paths is then sensitized so as to detect all single stuck-at faults. The authors demonstrated that the one-hot encoded FSMs can be easily and thoroughly tested via a simple algorithm. It is demonstrated that the use of scan paths is not necessary if a one-hot encoded state assignment is made. The synthesis and simulation resulting have shown that the package of one-hot encoding and branch testing constitutes a viable design and test approach

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Computers, IEEE Transactions on  (Volume:40 ,  Issue: 6 )