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Combination of TCAD and physical MOSFET model for LSI development time reduction

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11 Author(s)
Ishimaru, K. ; Memory LSI R&D Center, Toshiba Corp., Yokohama, Japan ; Kasai, K. ; Fukaura, Y. ; Okayama, Y.
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Advantage of MOSFET SPICE parameter prediction by combining TCAD and BSIM3 model is presented. This method can release sufficient SPICE parameters without wafer fabrication. Lithography TCAD can reduce pattern optimization work. Device development time reduction is also presented with fabricated SRAM results

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Advanced Semiconductor Manufacturing Conference and Workshop, 2000 IEEE/SEMI

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