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The high leakage current in deep submicron, short-channel transistors can increase the stand-by power dissipation of future IC products and threaten well established quiescent current (I/sub DDQ/)-based testing techniques. This paper reviews transistor intrinsic leakage mechanisms. Then, these well-known device properties are applied to a test application that combines I/sub DDQ/ and ICs maximum operating frequency (F/sub max/) to establish a novel two-parameter test technique for distinguishing intrinsic and extrinsic (defect) leakages in ICs with high background leakage. Results show that I/sub DDQ/ along with F/sub max/ can be effectively used to screen defects in high performance, low V/sub T/ (transistor threshold voltage) CMOS ICs.