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A compact physical via blockage model

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4 Author(s)
Qiang Chen ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; Davis, J.A. ; Zarkesh-Ha, P. ; Meindl, J.D.

Via blockage due to signal interconnects and its impact on wirability of multi-billion-transistor chips are systematically analyzed. Via classifications are introduced. By taking advantage of a stochastic interconnect length distribution and a multi-level interconnect network architecture, a physical via blockage model exploiting channel availability is proposed. This model reveals that the most severe via blockage occurs on first metal level, wasting more than 10% and up to about 50% of wiring area. A new perspective on chip size limit imposed by via blockage is also provided by using the proposed model.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:8 ,  Issue: 6 )