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A wide variety of models for estimating the distribution of on-chip net lengths assume an accurate estimate for an empirical parameter called the Rent exponent. Due to its definition as an exponent, these models are sensitive to its precise value, and careful selection is essential for good estimates of layout requirements and cycle times. In addition, it is also important to be able to predict changes in the Rent exponent with (possibly discontinuous) changes in interconnect technology. This paper presents a range of methods for estimating the Rent exponents of arbitrarily large gate placements as a function of optimization procedure and the level of fan-out present in the netlist. The first part of the paper describes a rapid algorithmic approach which combines the self-similar, or fractal attributes of small wiring cells with a Monte Carlo sampling method. This method is shown to accurately account for variations in both the wiring signature of the netlist and for the effects of most algorithms used for placement optimization. The second part of the paper presents an analytical model for Rent exponent prediction, based on a renormalization group transformation. This transformation is designed to filter out information which does not contribute to the scale-invariant properties of the optimized netlist enabling the derivation of a closed-form expression for the Rent exponent.