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System-level performance evaluation of three-dimensional integrated circuits

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2 Author(s)
Rahman, Arifur ; Microsystems Technol. Lab., MIT, Cambridge, MA, USA ; Reif, Rafael

In this paper, the wire (interconnect)-length distribution of three-dimensional (3-D) integrated circuits (ICs) is derived using Rent's rule and following the methodology used to estimate two-dimensional (2-D) (wire-length distribution). Two limiting cases of connectivity between logic gates on different device layers are examined by comparing the wire-length distribution and average and total wire-length. System performance metrics such as clock frequency, chip area, etc., are estimated using wire-length distribution, interconnect delay criteria, and simple models representing the cost or complexity for manufacturing 3-D ICs. The technology requirement for interconnects in 3-D integration is also discussed.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:8 ,  Issue: 6 )