By Topic

High-speed on-chip ECC for synergistic fault-tolerance memory chips

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
J. A. Fifield ; IBM Gen. Technol. Div., Essex Junction, VT, USA ; C. H. Stapper

The placement of error-correcting-code (ECC) systems on dynamic-RAM (DRAM) chips poses many practical problems, among which are increased access time and chip size. The authors describe an optimized, self-contained, and self-timed on-chip ECC system embedded in a high-speed 16-Mb DRAM chip. This chip also has redundant word and bit lines. The combination of redundancy and on-chip ECC produces a synergistic effect which results in a major increase in fault tolerance for the hard manufacturing defects. It also improves the reliability of the chip, regardless of manufacturing defects. This improvement is attained with only a 5-ns penalty in access time and an 11% increase in chip size

Published in:

IEEE Journal of Solid-State Circuits  (Volume:26 ,  Issue: 10 )