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A 30-b integrated logarithmic number system processor

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2 Author(s)
L. K. Yu ; Dept. of Electr. Eng., Toronto Univ., Ont., Canada ; D. M. Lewis

The authors describe an integrated processor that performs addition and subtraction of 30-b numbers in the logarithmic number system (LNS). This processor offers 5-MOPS performance in 3-μm CMOS technology, and is implemented in a two-chip set comprising 170 K transistors. Two techniques are used to achieve this precision in a moderate circuit area. Linear approximation of the LNS arithmetic functions using logarithmic arithmetic is shown to be simple due to the particular functions involved. A segmented approach to linear approximation minimizes the amount of table space required. Subsequent nonlinear compression of each lookup table leads to a further reduction in table size. The result is that a factor of 285 reduction in table size is achieved, compared to previous techniques. The circuit area of the implementation is minimized by optimizing the table parameters, using a computer program that accurately models ROM area. The implementation is highly pipelined, and produces one result per clock cycle using a ten-stage pipeline

Published in:

IEEE Journal of Solid-State Circuits  (Volume:26 ,  Issue: 10 )