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A low-power analog correlation processor for real-time camera alignment and motion computation

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1 Author(s)
McIlrath, L.G. ; Artificial Intelligence Lab., MIT, Cambridge, MA, USA

A design is presented for a low-power switched-current block correlation processor, which produces a set of feature matches between pairs of binary edge images. The novelty and usefulness of the processor stem from the reliability of its outputs. Statistical tests are included to minimize the probability that the correspondences found have occurred by chance. The results may be used without further refinement to accurately compute the epipolar geometry between two camera positions. The primary applications of this processor are computing camera motion and providing coarse alignment of two images acquired from similar sensors. An analog design was chosen to reduce circuit area in order to accommodate both large template blocks and search areas. Switched current sources at each pixel are summed on a single wire, while analog comparators implement the validation tests and track the minimum score. A prototype 5×5 block processor with a 9×9 search area was fabricated as a “Tiny Chip” through MOSIS in a 1.2-μm complimentary metal-oxide-semiconductor (CMOS) process. The chip correctly determined the correct matches for the given patterns and dissipated no more than 12 μW of static power per pixel in continuous operation. In a full-scale implementation, an array of several large (e.g., 24×24) block processors could be placed single 1 cm2 die. Measurements indicate that the computations for each block offset can be processed in less than 200 ns, implying that a 200×200 area can be searched in 8 ms

Published in:

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on  (Volume:47 ,  Issue: 12 )

Date of Publication:

Dec 2000

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