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An efficient implementation of BIST for floating point DSP processor

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3 Author(s)
Jaeheung Park ; Dept. of Comput., Soongsil Univ., South Korea ; Hoon Chang ; Ohyoung Song

In this paper, we describe the implementation of BIST technique which is applied to enhance the reliability of the FLOVA chip i.e., the floating point DSP core for processing graphic data and 3D graphics. In order to enhance the reliability of FLOVA, we adopt the BIST technique for floating-point modules which have complicated logic. For embedded data and program memory, we adopt the memory BIST technique. The boundary scan technique, providing board-level testing and to control BIST logic, has been also implemented

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ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on

Date of Conference: