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In this paper, an implementation method to optimize a 1024-bit RSA processor is presented. Basically, the Montgomery algorithm is used and modified considering the large bit modular multiplication. We propose a new architecture for 1024-bit RSA processing in order to reduce the required hardware resources. The new architecture is also fit for an effective I/O interface. We have implemented a single-chip 1024-bit RSA processor based on the modified algorithm and architecture with 0.65-μm SOG technology using Verilog HDL. As a result, it is shown that the processor can perform 1024-bit RSA operation in less than 43 ms at 50 MHz
Published in:
ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on
Date of Conference: 2000
- Page(s):
- 187 - 190
- Meeting Date :
- 28 Aug 2000-30 Aug 2000
- Print ISBN:
- 0-7803-6470-8
- INSPEC Accession Number:
- 6866793
- Conference Location :
- Cheju
- Digital Object Identifier :
- 10.1109/APASIC.2000.896940
- Product Type:
- Conference Publications
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