Cart (Loading....) | Create Account
Close category search window
 

Deterministic test pattern generation techniques for sequential circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Hamzaoglu, I. ; Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA ; Patel, J.H.

This paper presents new test generation techniques for improving the average-case performance of the iterative logic array based deterministic sequential circuit test generation algorithms. To be able to assess the effectiveness of the proposed techniques, we have developed a new ATPG system for sequential circuits, called ATOMS, and we have incorporated these techniques into the test generator ATOMS achieved very high fault coverages in a short amount of time for the ISCAS89 sequential benchmark circuits, demonstrating the effectiveness of these techniques on the test generation performance.

Published in:

Computer Aided Design, 2000. ICCAD-2000. IEEE/ACM International Conference on

Date of Conference:

5-9 Nov. 2000

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.