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Pipeline optimization for asynchronous circuits: complexity analysis and an efficient optimal algorithm

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2 Author(s)
Sangyun Kim ; Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA ; Beerel, P.A.

This paper addresses the problem of identifying the minimal pipelining needed in an asynchronous circuit (e.g., number/size of pipeline stages/latches required) to satisfy a given performance constraint, thereby implicitly minimizing area and power for a given performance. In contrast to the somewhat analogous problem of retiming in the synchronous domain, we first show that the basic pipeline optimization problem for asynchronous circuits is NP-complete. This paper then presents an efficient branch and bound algorithm that can find the optimal pipeline configuration for moderately-sized problems. Our experimental results on a few scalable system models demonstrate that our novel branch and bound solver can find the optimal pipeline configuration for models that have up to 2/sup 35/ possible pipeline configurations.

Published in:

Computer Aided Design, 2000. ICCAD-2000. IEEE/ACM International Conference on

Date of Conference:

5-9 Nov. 2000