By Topic

Quantitative method for evaluating quality of analogue VLSI layout

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Wu, P.B. ; Dept. of Electron. Syst. Eng., Essex Univ., Colchester, UK ; Mack, R.J. ; Massara, R.E.

A quantitative benchmarking metric is presented for the evaluation of the quality of analogue layout. It facilitates comparisons between alternative design automation tools and, for a given tool, provides assessment of each layout instance. The quality metric reflects two principal concerns in layout design: area efficiency and net routing optimality. The algorithm has been developed to accommodate hierarchical structures, as well as flat designs. The metric allows the designer to alter the relative importance of area and routing efficiencies, although a recommendation is given on the appropriate balance. The results demonstrate the use of the metric to evaluate an automatic layout tool, and its effectiveness in providing a characterisation that corresponds to the expert designer's judgement

Published in:

Circuits, Devices and Systems, IEE Proceedings -  (Volume:147 ,  Issue: 6 )