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An optimal hardware-algorithm for sorting using a fixed-size parallel sorting device

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3 Author(s)
Olarlu, S. ; Dept. of Comput. Sci., Old Dominion Univ., Norfolk, VA, USA ; Pinotti, M.C. ; Si Qing Zheng

We present a hardware-algorithm for sorting N elements using either a p-sorter or a sorting network of fixed I/O size p while strictly enforcing conflict-free memory accesses. To the best of our knowledge, this is the first realistic design that achieves optimal time performance, running in Θ(NlogN/plogp) time for all ranges of N. Our result completely resolves the problem of designing an implementable, time-optimal algorithm for sorting N elements using a p-sorter. More importantly, however, our result shows that, in order to achieve optimal time performance, all that is needed is a sorting network of depth O(log2p) such as, for example, Batcher's classic bitonic sorting network

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Computers, IEEE Transactions on  (Volume:49 ,  Issue: 12 )