By Topic

Asymptotically tight bounds for computing with faulty arrays of processors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

8 Author(s)
Kaklamanis, C. ; Aiken Comput. Lab., Harvard Univ., Cambridge, MA, USA ; Karlin, A.R. ; Leighton, F.T. ; Milenkovic, V.
more authors

The computational power of 2-D and 3-D processor arrays that contain a potentially large number of faults is analyzed. Both a random and a worst-case fault model are considered, and it is proved that in either scenario low-dimensional arrays are surprisingly fault tolerant. It is also shown how to route, sort, and perform systolic algorithms for problems such as matrix multiplication in optimal time on faulty arrays. In many cases, the running time is the same as if there were no faults in the array (up to constant factors). On the negative side, it is shown that any constant congestion embedding of an n×n fault-free array on an n×n array with Θ( n2) random faults (or Θ(log n) worst-case faults) requires dilation Θ(log n). For 3-D arrays, knot theory is used to prove that the required dilation is Ω(√log n)

Published in:

Foundations of Computer Science, 1990. Proceedings., 31st Annual Symposium on

Date of Conference:

22-24 Oct 1990