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Design methodology of a robust ESD protection circuit for STI process 256 Mb NAND flash memory

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3 Author(s)
Ikehashi, T. ; Adv. Memory Design Group, Toshiba Corp. Semicond. Co., Yokohama, Japan ; Imamiya, K. ; Sakui, K.

With the use of a device simulator, we show that an ESD protection circuit whose junction filled with contacts is suited to a scaled STI process having thin n- junction with n+ being implanted from contact holes. We have confirmed by measurements that the protection has sufficient robustness

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Electronics Packaging Manufacturing, IEEE Transactions on  (Volume:23 ,  Issue: 4 )