By Topic

Functionally testable path delay faults on a microprocessor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Wei-Cheng Lai ; Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA ; Krstic, A. ; Kwang-Ting Cheng

The impact of delay defects on these functionally untestable paths on overall circuit performance involves identification of such paths determining the achievable path delay fault coverage and reducing the subsequent test generation effort. The experimental results for two microprocessors (Parwan and DLX) indicate that a significant percentage of structurally testable paths are functionally untestable

Published in:

Design & Test of Computers, IEEE  (Volume:17 ,  Issue: 4 )