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High-level low power FPGA design methodology

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4 Author(s)
Wolff, F.G. ; Dept. of Electr. Eng. & Comput. Sci., Case Western Reserve Univ., Cleveland, OH, USA ; Knieser, M.J. ; Weyer, D.J. ; Papachristou, C.A.

High-level design for low power is difficult to accomplish especially for FPGA designs. Presents a design technique that uses pre-computed tables that characterize the RTL and Intellectual Property (IF) components to estimate power. Actual tables were computed and the low-power design technique demonstrated. The results show that a lower power design can be achieved given this design methodology

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National Aerospace and Electronics Conference, 2000. NAECON 2000. Proceedings of the IEEE 2000

Date of Conference: