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Novel technique for built-in self-test of FPGA interconnects

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4 Author(s)
Xiaoling Sun ; Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada ; Xu, S. ; Ben Chan ; Trouborst, P.

This paper presents the first BIST approach for testing interconnects of SRAM-based FPGAs using error control coding. The proposed scheme requires a total of six test configurations and has superior multiple fault coverage on wire segment stuck-at, stuck-open and bridging faults, programmable switch stuck on/off faults, and the combinations of these faults in global routing resources

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Test Conference, 2000. Proceedings. International

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