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An approach to testing 200 ps echo clock to output timing on the double data rate synchronous memory

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2 Author(s)
Van Dinh, D. ; Semicond. Products Sector, Motorola Inc., Austin, TX, USA ; Rabitoy, V.

This paper describes an approach to testing DDR echo clock outputs and transfer data specifications. Tester accuracy issues create difficulty in guaranteeing the 200 ps spec timing between these two groups of outputs. This approach will find the balance between accurate testing and test costs

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Test Conference, 2000. Proceedings. International

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