By Topic

A framework to evaluate test tradeoffs in embedded core based systems-case study on TI's TMS320C27xx

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
J. Abraham ; Texas Instrum. (India) Ltd., Bangalore, India ; N. Prasad ; S. Chakravarthy ; A. Bagwe
more authors

Intellectual property cores are being widely used to enable rapid integration of entire systems onto chips. While allowing for rapid system prototyping and design, this methodology complicates the problem of testing them. Various design for test techniques and guidelines are evolving across design groups for embedded core based systems. This paper discusses a framework: for evaluating these techniques and the tradeoffs therein, to drive a cost effective test methodology. Its main contributions include: (i) it inspects various techniques to improve the test coverage and test quality in embedded core based systems. (ii) It explains important test cost measures, and proposes a framework for making design time decisions to minimise the cost. (iii) It presents the results of various experiments carried out on representative DSP core based systems, built around Texas Instruments' new DSP core, TMS320C27xx. These results have highlighted various design, and test tradeoffs, and are being profitably used to drive a cost effective test methodology on newer cores and devices

Published in:

Test Conference, 2000. Proceedings. International

Date of Conference: