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Test generation for path-delay faults in one-dimensional iterative logic arrays

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2 Author(s)
Abdulrazzaq, N.M. ; Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA ; Gupta, S.K.

We propose a test generation method for path-delay faults in combinational iterative logic arrays (ILAs). The number of paths as well as the number of critical paths in ILAs can grow exponentially with the number of stages. Existing path-delay test generation techniques explicitly target each selected path and cannot generate tests for ILAs with reasonable numbers of stages, e.g., 16 and 32. The proposed method overcomes this difficulty by implicitly targeting all testable paths and can generate tests for ILAs of arbitrary size and guarantees coverage of all testable faults. The proposed method also drastically decreases the test data volume to be stored in the high-speed memories in the probe unit of the tester by generating tests in the form of a small number of expressions. This is of great benefit since the ability to store large volumes of test data is a significantly greater limiting factor than the time required to apply the tests. Finally, for most ILAs, this method produces a compact set of tests

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Test Conference, 2000. Proceedings. International

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