By Topic

Si-emulation: system verification using simulation and emulation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Zan Yang ; Dept. of Electr. Eng., Texas A&M Univ., USA ; Min, B. ; Gwan Choi

A system-level verification framework is presented that combines the speed of hard-wired (FPGA-based) emulation and the observability of gate-level simulation. A checkpoint approach is developed for (1) periodic capturing of the machine state from an emulation, (2) sampling of the emulation output for error detection, and (3) constructing a piece-wise simulation run, necessary to debug the design in an event of an error detection from the emulation. The checkpoint frequency is optimized to reduce the cost of downloading the state data during a hardware emulation. A sampling of the emulation output also minimizes the network-bandwidth and storage-space requirements associated with instrumenting for error detection

Published in:

Test Conference, 2000. Proceedings. International

Date of Conference:

2000