By Topic

Delay-fault testing and defects in deep sub-micron ICs-does critical resistance really mean anything?

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Moore, W. ; Dept. of Eng. Sci., Oxford Univ., UK ; Gronthoud, G. ; Baker, K. ; Lousberg, M.

This paper reflects on some recent results that show the value of delay-fault tests on a deep sub-micron process. However, the results also suggest that untargetted test patterns perform almost as well as those targetted on a transition fault model, despite appearing to have a much lower fault coverage. This leads to an examination of the defect mechanisms in deep sub-micron ICs, in particular the relationship of crosstalk and power-rail coupling to resistive opens and resistive bridges. A number of new fault mechanisms are described. The paper shows the importance of initialization conditions for resistive opens and the importance of noise margins with resistive bridges. These noise margin considerations throw doubts on the idea used by other authors of the “critical resistance” of a bridge

Published in:

Test Conference, 2000. Proceedings. International

Date of Conference:

2000