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Memory efficient software synthesis with mixed coding style from dataflow graphs

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2 Author(s)
Wonyong Sung ; CAP Lab., Seoul Nat. Univ., South Korea ; Soonhoi Ha

This paper presents a set of techniques to reduce the code and data sizes for software synthesis from graphical digital signal-processing programs based on the synchronous dataflow model. By sharing the kernel code among multiple instances of a block with a shared function, we can further reduce the code size below the previous results based on inline coding style. A systematic approach also is devised to give up the single appearance schedule for reducing the data buffer requirement. The proposed techniques have been evaluated with two real-life examples to prove their significance.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:8 ,  Issue: 5 )

Date of Publication:

Oct. 2000

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