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Optimized synthesis of self-testable finite state machines

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2 Author(s)
B. Eschermann ; Inst. fuer Rechnerentwurf & Fehlertoleranz, Karlsruhe Univ., West Germany ; H. -J. Wunderlich

A synthesis procedure for self-testable finite state machines is presented. Testability comes under consideration when the behavioral description of the circuit is being transformed into a structural description. To this end, a novel state encoding algorithm, as well as a modified self-test architecture, is developed. Experimental results show that this approach leads to a significant reduction of hardware overhead. Self-testing circuits generally employ linear feedback shift registers for pattern generation. The impact of choosing a particular feedback polynomial on the state encoding is discussed.<>

Published in:

Fault-Tolerant Computing, 1990. FTCS-20. Digest of Papers., 20th International Symposium

Date of Conference:

26-28 June 1990