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TOF: a tool for test pattern generation optimization of an FPGA application oriented test

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5 Author(s)
Renovell, M. ; LIRMM-UM2, Montpellier, France ; Portal, J.M. ; Faure, P. ; Figueras, J.
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The objective of this paper is to generate an Application-Oriented Test Procedure to be used by a FPGA user in a given application. General definitions concerning the specific problem of testing RAM-based FPGAs are first given such as the important concept of `AC-non-redundant fault.” Then, it is commented that a classical test pattern generation performed on the circuit netlist gives a low AC-non-redundant fault coverage and it is pointed out that test pattern generation performed on a FPGA representation is required. It is also commented that test pattern generation performed on the FPGA representation can be significantly accelerated by different techniques. A procedure called TOF is described to validate the proposed approach on benchmark circuits

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Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian

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