By Topic

Reducing test application time for full scan circuits by the addition of transfer sequences

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Pomeranz, I. ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; Reddy, S.M.

A test set for scan designs may consist of tests where primary input vectors are embedded between a scan-in and a scan-out operation. A static compaction procedure proposed earlier reduces the test application time of such a test set by removing the scan operations at the end of one test and at the beginning of another test, and concatenating the primary input vectors of the two tests. In this work, we investigate a method to increase the number of tests that can be combined in this way, thus further reducing the number of scan operations and the test application time. This is done by inserting one or more primary input vectors between the two tests being combined. The inserted vectors help detect faults that were originally detected due to the scan operations, allowing us to combine tests that cannot be combined otherwise. We present experimental results to demonstrate that improved levels of compaction can be achieved by this method

Published in:

Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian

Date of Conference: