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On the feasibility of fault simulation using partial circuit descriptions

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2 Author(s)
I. Pomeranz ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; S. M. Reddy

We investigate the feasibility of performing fault simulation for gate-level circuits using only subcircuits, without considering the complete circuit. This approach can be used to reduce the memory requirements during fault simulation of large circuits. Subcircuits for fault simulation are defined based on subsets of state variables. For every subset of state variables V, only the input cones of next state variables in V are included in the subcircuit being simulated, as well as input cones of primary outputs. We present experimental results to demonstrate the feasibility of fault simulation using subcircuits

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Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian

Date of Conference: