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Test generation for fault isolation in analog circuits using behavioral models

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2 Author(s)
S. Cherubal ; Georgia Inst. of Technol., Atlanta, GA, USA ; A. Chatterjee

Test generation techniques to isolate failures to different parts of an analog circuit, have relied on a list of failure modes being available for the circuit being tested. This may be difficult to obtain for general analog circuits. In this paper we propose a new methodology for isolation of parametric failures in analog circuits that (a) does not require a fully specified fault list, (b) is able to work with high-level behavioral descriptions of the various sub-modules of the CUT (c) is able to isolate faults caused by multiple parameter variations in the CUT and (d) is robust in the presence of measurement noise and manufacturing tolerances of analog components. Experimental results to demonstrate the effectiveness of the proposed technique are presented

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Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian

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