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Pseudo-nMOS revisited: impact of SOI on low power, high speed circuit design

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5 Author(s)
Subba, N. ; Dept. of Electr. & Comput. Eng., George Mason Univ., Fairfax, VA, USA ; Salman, A. ; Mitra, S. ; Ioannou, D.E.
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Bulk pseudo-nMOS (i.e. CMOS with grounded pMOS pullup device) circuits have been quite popular in the past because they are fast, small and pMOS devices are good pullup resistive loads. A pseudo-nMOS gate with a fan-in of N requires only N+1 transistors (as opposed to 2N for standard CMOS), resulting in smaller area as well as smaller parasitic capacitances, whereas each input connects to only one transistor, presenting a smaller load to the preceding gate. Since these advantages come at the expense of static power consumption, pseudo-nMOS circuits have often lost their appeal for large circuits, even though they are frequently used in some critical path elements when speed and area are at a premium (Weste and Eshraghian, 1993). If a weaker pMOS load transistor could be used without sacrificing speed, for example by reducing the load on the dotted node (either due to smaller devices in the pulldown tree, or to a smaller driven load representing a similar gate), the static power could be minimized. Since from a circuit designer's perspective, one of the major advantages of SOI technology is the reduction of junction capacitance, this paper takes a fresh look at pseudo-nMOS and finds that SOI technology makes possible important performance (speed and power) and area improvements and predicts that it can be used widely in the design of SOI custom-integrated circuits

Published in:

SOI Conference, 2000 IEEE International

Date of Conference:

2000