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High performance real-time neural scheduler for ATM switches

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4 Author(s)
J. M. Pousada-Carballo ; Dept. de Tecnologias de las Commun., Campus Univ. de Vigo, Spain ; F. J. Gonzalez-Castano ; P. S. Rodriguez-Hernandez ; U. M. Garcia-Palomares

Input-buffered asynchronous transfer mode (ATM) packet switches are simpler than output-buffered switches. However, due to HOL blocking, their throughput is poor. Neural schedulers represent a promising solution for high throughput input-buffered switching, but their response time variance is too high for realistic hard real-time constraints. To overcome this problem, we formulate and evaluate a new neural scheduler with bounded response time.

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IEEE Communications Letters  (Volume:4 ,  Issue: 11 )