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5-GHz CMOS radio transceiver front-end chipset

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2 Author(s)
Ting-Ping Liu ; Lucent Technol. Bell Labs., Holmdel, NJ, USA ; E. Westerwick

Incorporating the direct-conversion architecture, a 5-GHz band radio transceiver front end chipset for wireless LAN applications is implemented in a 0.25-/spl mu/m CMOS technology. The 4-mm/sup 2/ 5.25-GHz receiver IC contains a low noise amplifier with 2.5-dB noise figure (NF) and 16-dB power gain, a receive mixer with 12.0 dB single sideband NF, 13.7-dB voltage gain, and -5 dBm input 1-dB compression point. The 2.7-mm/sup 2/ transmitter IC achieves an output 1-dB compression of -2.5 dBm at 5.7 GHz with 33.4-dB (image) sideband rejection by using an integrated quadrature voltage-controlled oscillator. Operating from a 3-V supply, the power consumptions for the receiver and transmitter are 114 and 120 mW, respectively.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:35 ,  Issue: 12 )