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A CMOS nested-chopper instrumentation amplifier with 100-nV offset

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3 Author(s)
Bakker, A. ; Philips Semicond., Sunnyvale, CA, USA ; Thiele, K. ; Huijsing, J.H.

A CMOS nested-chopper instrumentation amplifier is presented with a typical offset of 100 nV. This performance is obtained by nesting an additional low-frequency chopper pair around a conventional chopper amplifier. The inner chopper pair removes the 1/f noise, while the outer chopper pair reduces the residual offset. The test chip is free from 1/f noise and has a thermal noise of 27 nV//spl radic/Hz consuming a total supply current of 200 /spl mu/A.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:35 ,  Issue: 12 )